The present invention relates generally to a method, system, and computer program product for computer aided allocation of physical memory of a computer system, and more particularly to a method, system, and computer program product for allocating physical memory based on required system architecture specifications, system configuration, and user requirements.
A Memory Management Unit, (hereinafter “MMU”), of the computer system, manages access to memory in computer hardware. The MMU performs virtual memory management by translating virtual memory addresses to physical addresses in computer system memory. The MMU may also be referred to as a paged memory management unit, (hereinafter “PPMU”). The MMU may be part of a Central Processing Unit, (hereinafter “CPU”), or alternatively may be a separate integrated circuit. Additional functions performed by the MMU include managing functional attributes of the memory, such as bus arbitration, memory protection, cache control, and bank switching in some computer architectures, such as 8-bit systems.
The MMU typically divides a virtual address space, which is a range of addresses used by the processor, into pages. A basic unit for memory translation is called a page. The attributes of a physical page in memory are specified within the translation resources of a page, such that each address within a page comprises identical attributes. Example of page sizes include 4 kilobyte, (hereinafter “kB”), 16 kB, 64 kb, 2 megabyte, (hereinafter “MB”), 32 MB, 512 MB, and 1 gigabyte. Upper address bits of a virtual address comprise a virtual page number, while a bottom bit of the virtual address corresponds to an offset within a page.
An MMU may use a page table containing one page table entry, (hereinafter “PTE”) per page. The page table maps virtual page numbers to main memory physical page numbers. A physical page number is combined with a page offset to give a complete physical address. The PTE may identify information regarding a page, the information may include whether or not the page has been written to, a last assessed date stamp, identification of a processor type which may read and write to the page, for example in supervisor mode or in user mode, and whether the page should be cached. The PTE may prohibit access to a virtual page, for example by directing the MMU to signal a page fault to the CPU. This may occur when there is no physical memory allocated to that virtual page. An operating system, (hereinafter “OS”), may manage the page fault, for example by accessing available physical memory, and creating a new PTE to map the available physical memory to the requested virtual address. If there is no available physical memory, the OS may select an existing page, use a replacement algorithm, and save the existing page to a disk (a process called “paging”). A shortage of PTEs, may result in the OS having to free memory for new mapping. Physical memory may include a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any other method of storing computer code. Memory types may include the physical memory examples listed above.
The MMU may generate an illegal access error condition or an invalid page fault condition upon illegal or non-existing memory accesses, respectively, which may lead to an exception fault or a bus error condition, when handled by the operating system.
An exerciser tool, or an exerciser, may be used in a post-silicon validation or verification cycle as part of a manufacturing process of Integrated Circuits, (hereinafter “IC”). Post-silicon verification confirms functionality of actual devices running in real time using tools such as a logic analyzer and other assertion based tools. An exerciser is an application that is loaded onto a Device or Design Under Test (DUT), and may generate a test program, alternatively called a test case or test template, execute the test program, and check a result of the test program. Exercisers are essential tools in functional verification of a post-silicon platform. An exerciser is an application or program loaded to the computer system, which continuously generates test-cases, executes the test cases, and checks results of the test cases. A stimuli generator is a subcomponent of the exerciser used to generate a test case. As part of test case generation, the stimuli generator allocates one or more intervals in physical memory to be used for testing, and generates virtual translations for each of the one or more intervals.
In a post-silicon test environment, an amount of physical memory available to use for testing may be limited. For example, at an early stage of post-silicon testing, memory devices that are external to a processor may not be available and the processor is required to run the post-silicon testing from its own memory cache. Allocation of intervals in memory is limited when a test case requires many intervals of memory, each with different attributes. For later verification stages, the exerciser may use memory which is external to the processor. It is important that a test case includes memory translations with a variety of page sizes. It is typically desired that certain intervals are translated with large pages in order to control data flow of specific translation micro-architecture resources. For extensive verification it is also desired that an allocation of intervals covers all the physical memory.
Each interval has specific memory attributes. Hence, translating intervals with large pages imposes constraints for allocation of the intervals, since memory attributes are consistent across all pages within the interval, where pages of different sizes can overlap each other in the physical memory domain.